Find jobs in AI/ML, Data Science and Big Data
13 results
for Power Integrity
(Skill/Tech stack)
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Director, Embedded Memory EUR 91K-120KAdvanced nodes | Automation | Automation Development | BTI | Bitcell DesignFinancial benefits | Hybrid office location | Industry conference visibility | Medical benefits | Team leadership developmentExecutive-level Full TimeMontbonnot-Saint-Martin, Auvergne-Rhône-Alpes, France R2d ago
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Manager: Embedded Electronics & PCBA Design CoE INR 2500K-4000KANSYS | Agile | CAM Editing | CAM Validation | CAM350Senior-level Full TimeHadapsar, Pune, Maharashtra, IND, 4110133d ago
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ANSYS SiWave | Altium Designer | Analog circuit | Analog circuit design | Cadence AllegroSenior-level Full TimeRedmond, WA | Burlingame, CA11d ago
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Staff GenAI Engineer - Early PDN Modeling USD 170K-290KCurrent Density | Data Analysis | Drop Analysis | EDA Tools | Electromigration RiskMedical, dental, vision plans | Paid Holidays | Paid family leave | Paid time offSenior-level Full TimeSan Jose, CA, United States11d ago
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AMS/RF Board Designer, Quantum AI USD 159K-230KASIC design | Analog circuit | Analog circuit design | Board Design | Board-level designMid-level Full TimeGoleta, CA, USA14d ago
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DRAM | Design for test | Design verification | HBM | IP integrationSenior-level Full TimeSunnyvale, CA, USA18d ago
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Senior Manager, Embedded Memory USD 146K-223KArea Optimization | Automation | BTI | Bitcell Design | Body BiasSenior-level Full TimeHai Chau, Da Nang, Vietnam1mo ago
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Senior Embedded Hardware Engineer SGD 74K-120KAnalog and Mixed Signal | Analog and mixed-signal design | Bill of Materials | Blind Via | Buried ViaSenior-level Full TimeSingapore, Singapore1mo ago
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Senior-level Full TimeMontbonnot-Saint-Martin, Auvergne-Rhône-Alpes, France1mo ago
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Embedded Systems Engineer — Autopilot Hardware EUR 43K-60KAgile Scrum | Altium Designer | Analog electronics | Boundary Scan | CANEmployee Assistance Programme (EAP) | Health insurance | Meal allowance | Shuttle transportMid-level Full TimePorto, Portugal1mo ago
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Automation | EMIR analysis | Formal verification | FusionCompiler | IR-DropSenior-level Full TimeCupertino, California, USA1mo ago
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Design Technology Co-Optimization Engineer USD 138K-198KCMOS device physics | Datacenter IP blocks | Design Rule Manual | Design rule | Device physicsMid-level Full TimeSunnyvale, CA, USA1mo ago
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Circuit design | EM analysis | Emulation | Gate-level | Gate-level netlist401k matching | Dental insurance | Health insurance | Paid time off | Parental leaveSenior-level Full TimeCupertino, California, USA1mo ago