Machine Learning Design Engineer, Silicon
Bengaluru, Karnataka, India
INR 3400K-5000K (estimate) Senior-level Full Time
Tasks
- Apply code review testing refactoring
- Define digital logic specifications
- Ensure design functionality
- Implement digital logic using Chisel
- Implement digital logic using SystemVerilog
- Implement digital logic using Verilog
- Perform power area performance trade offs
- Set technical direction
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC design | Area Optimization | Assertion-based Formal Verification | CHISEL | Cache | Cache coherence | DFT | DRAM | Digital Logic | Digital Logic Design | FPGA design | Formal verification | Hardware verification | Logic Design | Logic synthesis | Low power | Low power design | Machine Learning | Memory compression | Performance optimization | Perl | Power Optimization | Power analysis | Power design | Python | RTL design | Scripting | SoC Architecture | SystemVerilog | Timing Analysis | Verilog
Education
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