Director, Digital Compute & Power Optimization
Tasks
- Close timing for high performance ASICs
- Conduct silicon bring-up and debug
- Develop micro architecture for ASICs
- Execute block level verification
- Implement design for test
- Insert scan test
- Integrate IP blocks
- Lead RTL development
- Manage RTL design engineers
- Optimize low power design
- Perform simulations
- Run synthesis
Perks/Benefits
- N/A
Skills/Tech-stack
ASIC | Automation | Bring-up | C# | CMOS | CMOS 28nm | CXL | Cadence | DDR | DFT | Equalizer Optimization | Ethernet | GLS | IP integration | Low power | Low power design | Microarchitecture | PCIe | Power design | Python | RTL | Scripting | SerDes | Silicon bring-up | Silicon debug | Simulation | Stuck at test | Stuck-at | Synopsys | Synthesis | Timing closure | Transition scan | UVM
Education
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