AI/ML Logic Design Engineer-Senior
Austin, Texas, United States of America
USD 127K-190K Senior-level Full Time
Tasks
- Conduct Static Timing Analysis
- Debug and optimize EDA tool flows
- Design microarchitecture for Hexagon NPU
- Develop RTL in SystemVerilog
- Estimate power performance area
- Perform end to end verification from instruction set architecture to RTL
- Perform logic synthesis
- Validate design pipeline feasibility
Perks/Benefits
- N/A
Skills/Tech-stack
Digital design | EDA Tool | EDA tool debugging | Git | Instruction set | Instruction set architecture | Logic synthesis | Perl | Power Estimation | Power analysis | Python | RTL design | Shell Scripting | Static Power | Static Power Analysis | Static Timing | Static Timing Analysis | SystemVerilog | Timing Analysis | Tool debugging
Education
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