Software R&D Engineer, RTL Optimization Tools
US, CA, Santa Clara, United States
USD 136K-218K Senior-level Full Time
Tasks
- Analyze impact of RTL changes on timing power and DFT
- Collaborate with RTL design teams to deploy optimization solutions
- Develop clustering and tree covering algorithms for technology mapping
- Implement datapath and logic synthesis optimization methods
- Invent parallel graph based RTL traversal analysis and manipulation
- Suggest or implement RTL modifications using machine learning
Perks/Benefits
- N/A
Skills/Tech-stack
Adversarial Networks | C++ | Clock distribution | Clocking | Design for testability | Distributed Computing | Generative Adversarial Networks | Graph Neural Networks | I/O | I/O Optimization | Language Models | Large Language Models | Logic synthesis | MBIST | Memory Optimization | Min Cost Tree Covering | Multithreading | Neural Networks | Power delivery | Power gating | RTL | Reinforcement Learning | SAT Solver | Scan Chain | Static Timing | Static Timing Analysis | SystemVerilog | Technology Mapping | Timing Analysis | VLSI | Verilog
Education
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Regions
Countries
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Cities
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