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Technical Lead Manager, Machine Learning, Memory Subsystem Design

Sunnyvale, CA, USA

USD 240K-333K Senior-level Full Time

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Found 8h ago
Tasks
Perks/Benefits
Skills/Tech-stack

Computer Architecture | DRAM | DRAM Memory Subsystem Design | DRAM memory | Design Methodology | Design for test | Design verification | HBM | Memory subsystem design | Physical Design | Power Integrity | Quality Control | RTL | RTL design | Semiconductor design | Signal Integrity | Silicon engineering | Silicon validation | Subsystem design | Verification Modeling

Education

Bachelor of Engineering | Bachelor of Science | Master of Science | PhD

Roles

Engineering Manager | Hardware Engineering Manager | Lead Manager | Machine Learning Hardware Engineering Manager | Manager | Technical Lead | Technical Lead Manager | Technical Manager

Regions

North America

Countries

United States

States

California, US

Cities

Sunnyvale, California, US

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