AI/ML ASIC Architect
Milpitas, CA, United States
USD 163K-249K (estimate) Senior-level Full Time
Tasks
- Analyze PPA tradeoffs and schedule targets
- Architect memory efficient inference training systems
- Author architecture specifications
- Collaborate with stakeholders and disseminate results
- Conduct post silicon performance analysis
- Create modular I/O subsystem architectures
- Define AI ML accelerator ASIC architecture specifications
- Define I/O subsystem and PCIe DMA architectures
- Define SoC subsystem and DMA hardware software firmware interactions
- Develop AI storage system architectures
- Drive frontend architecture for AI/ML accelerators
- Guide pre silicon design verification and post silicon validation
- Lead LLM workload analysis and characterization
- Perform hardware/software co-optimization
- Scope SoC requirements and define architectural requirements
Perks/Benefits
- N/A
Skills/Tech-stack
ARM | ASIC architecture | AXI interconnect | Area Optimization | Attention Mechanisms | CUDA | CXL | Cache optimization | Chunked prefill | Continuous batching | DMA | Design verification | Emulation | Endurance Analysis | Firmware | Flash Attention | GPU Architecture | HBM | Hardware/software | Hardware/software co-optimization | High Bandwidth | High Bandwidth Memory | I/O | I/O subsystem | KV cache | KV cache optimization | Memory controller | Microarchitecture | Mixture of Experts | Model Parallelism | NAND flash | NPU architecture | NVMe | Network on Chip | PCIe | PPA | Performance Engineering | Power analysis | Pruning | Quantization | RTL | Simulation | SoC | Speculative decoding | TPU architecture | Transformer Architecture | UCIe
Education
Roles
AI | AI ASIC Architect | AI Hardware Architect | ASIC Architect | Architect | Hardware Architect
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