ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration
Tasks
- Analyze microarchitectures and architectures
- Apply constraints
- Collaborate with verification and back-end teams
- Create microarchitectures
- Develop RTL designs
- Ensure timing clean design
- Implement SystemVerilog RTL
- Optimize area and power
- Perform Clock Domain Crossing Checks
- Perform lint checks
- Run synthesis
Perks/Benefits
Skills/Tech-stack
Architecture | Clock Domain | Clock Domain Crossing | Constraints | Domain crossing | Linting | Microarchitecture | RTL | Synthesis | SystemVerilog | Timing Analysis
Education
Regions
Countries
States
Cities
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