Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect
Tasks
- Design implement and review SystemVerilog designs
- Evaluate tradeoffs across microarchitecture and implementation
- Maintain microarchitecture documentation
- Optimize area power and timing
- Perform synthesis for area power timing estimation
- Translate architecture requirements into microarchitectures
Perks/Benefits
- Income protection benefits
- Medical, dental, vision plans
- Paid Holidays
- Paid family leave
- Paid time off
Skills/Tech-stack
Area Power Timing | C++ | Computer Architecture | Hardware Design | Memory systems | Microarchitecture | Python | RTL | SoC | Synthesis | SystemVerilog
Education
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