Director, Embedded Memory
EUR 91K-120K (estimate) Executive-level Full Time
Tasks
- Build and maintain memory IP benchmarks
- Conduct PPA analysis performance power area yield
- Define bitcell selection and peripheral architecture
- Drive circuit design and physical implementation
- Establish design verification and signoff methodology
- Lead integration debug and silicon correlation
- Lead memory compiler architecture
- Lead presales customer engagements and technical proposals
- Lead statistical and Monte Carlo analysis
- Manage DFT scan and BIST repair strategy
- Manage roadmap schedules dependencies and risks
- Mentor and grow memory design engineering team
- Optimize Vmin leakage performance area yield
- Perform customer issue root cause analysis
- Perform silicon validation and test chip development
- Represent company in foundry partner meetings and industry conferences
- Run what if and sensitivity analysis for architecture tradeoffs
- Support customer integration through tapeout and validation
- Translate SoC requirements into compiler specifications
Perks/Benefits
- Financial benefits
- Hybrid office location
- Industry conference visibility
- Medical benefits
- Team leadership development
Skills/Tech-stack
Advanced nodes | Automation | Automation Development | BTI | Bitcell Design | CDL | Corner analysis | DFT | DFT Scan | DRC | Dual Port RAM | EM | FastSPICE | FastScan | FinFET | GDSII | HCI | LEF | LVS | Leakage Optimization | Linux | Memory design | Monte Carlo | Monte Carlo Analysis | PVT Corner Analysis | Parasitic Extraction | Perl | Power Integrity | Python | ROM | Redhawk | Redundancy Repair | Register File | Reliability analysis | SPICE | SRAM | Self Timed Circuits | Sense Amplifier | TCL | Tessent | Verilog | Verilog modeling | Vmin Optimization | Vmin Yield Modeling | Write Driver | Yield modeling
Education
Roles
Design Lead | Director | Director Embedded Memory | Lead | Memory Design Lead
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