Machine Learning and Multimedia IP Verification Manager, Silicon
San Diego, CA, USA; Mountain View, CA, USA
USD 192K-279K Senior-level Full Time
Tasks
- Build constrained random verification environments
- Coordinate SoC and ML multimedia verification milestones
- Debug verification tests with design engineers
- Develop verification metrics and drive convergence
- Implement coverage analysis for stimulus and corner cases
- Lead and mentor verification engineers
- Manage verification test plans and regression simulation
- Plan verification for ML and multimedia hardware
Perks/Benefits
- N/A
Skills/Tech-stack
Constrained random | Constrained random verification | Control Status Registers | Coverage analysis | Formal verification | Hardware-software interface | Hardware/software | Low power | Low power verification | Object-Oriented | Object-oriented programming | Power Management | Power Verification | RTL | Random Verification | Regression testing | SoC integration | Software interface | SystemVerilog | SystemVerilog Assertions | Testbench development | UVM | Verification methodology
Education
Bachelor of Arts | Bachelor of Engineering | Bachelor of Science
Regions
Countries
States
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