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for SystemVerilog Assertions
(Skill/Tech stack)
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Staff Design Verification Engineer (AI/ML) USD 127K-175KAI/ML | Back Annotation | Behavioral Abstraction | Cadence JasperGold | Cadence XceliumSenior-level Full TimeUS, AZ, Chandler, East Elliot, United …10d ago
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Validation/Verification (UVM, Coverage, Agentic), Staff Engineer INR 2000K-2372KAI Assisted Verification | Code Coverage | Coverage analysis | Debugging | Functional CoverageSenior-level Full TimeHyderabad, India25d ago