Senior Member of Technical Staff, AI-optimized Memory SoC Microarchitect
Tasks
- Analyze PDN IR drop budgets
- Analyze thermal implications
- Collaborate with Physical Designers
- Compose microarchitecture documentation
- Define DFT architectures
- Define SoC floorplans
- Define SoC microarchitecture
- Define power delivery networks
- Define signal interfaces
- Drive clocking architectures
- Drive power sequencing
- Identify power hotspots
- Mitigate power hotspots
- Perform full chip area optimization
- Perform full chip energy optimization
- Perform full chip performance optimization
- Perform full chip power optimization
- Perform full chip timing optimization
- Set verification requirements
Perks/Benefits
- Dental insurance
- Income Protection for Disability
- Medical insurance
- Paid Holidays
- Paid family leave
- Paid time off
- Vision insurance
Skills/Tech-stack
Advanced packaging | Analog circuit | Analog circuit design | Chip packaging | Circuit design | Clocking architecture | DFT | Digital circuit | Digital circuit design | EDA Tools | Finite-state machines | Floorplanning | Grid Topology | IR-Drop | Interconnect | Microarchitecture specification | Power Delivery Network | Power Grid Topology | Power Hotspot Mitigation | Power delivery | Power grid | Power sequencing | RTL design | Scan Chain | Signal Interface | SoC Microarchitecture | Stacked Architecture | State machines | Static Timing | Static Timing Analysis | Synthesis | Thermal analysis | Timing Analysis | Verification planning
Education
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