Doktorand*in KI-Hardware-Architektur: Cache-Computing für LLMs (FPGA & ASIC)
Tasks
- Create formal models for memory compute tradeoffs
- Design RTL with SystemVerilog and VHDL
- Develop compute in cache architectures for LLM inference
- Measure performance and energy for verification
- Publish research at international conferences
- Run cycle accurate simulations
- Supervise bachelor and master theses
- Validate architectures on Xilinx AMD FPGAs
Perks/Benefits
- Conference participation
- Corporate discounts
- Employee retirement plan
- Family support benefits
- Flexible working hours
- Job ticket subsidy
- Mobile work
- Project coaching
Skills/Tech-stack
ASIC Design Flow | ASIC design | Cache Hierarchy | Cycle-accurate simulation | Design flow | FPGA | Formal modeling | In-memory) | Place and route | Processing in memory | Python | Python modeling | RISC-V | RTL design | Synthesis | SystemVerilog | Timing Analysis | Transformer Inference | VHDL | Xilinx AMD
Education
Roles
Regions
Countries
States
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