Senior Manager, Embedded Memory
USD 146K-223K (estimate) Senior-level Full Time
Tasks
- Conduct root cause analysis and issue resolution
- Conduct technical reviews and set team goals
- Coordinate integration debug and silicon correlation
- Define bitcell selection and peripheral architecture
- Drive circuit design and physical implementation
- Establish design verification and signoff methodology
- Lead and mentor memory design engineers
- Lead integration support through tapeout and validation
- Lead memory compiler architecture
- Lead silicon validation and test chip development
- Manage engineering schedules dependencies and risk
- Manage memory roadmap and methodology improvements
- Optimize Vmin leakage performance area and yield
- Perform PPA analysis and competitive benchmarking
- Run what if and sensitivity analysis for architecture tradeoffs
- Serve as senior technical lead in presales
- Translate customer requirements into compiler specifications and PPA commitments
Perks/Benefits
- N/A
Skills/Tech-stack
Area Optimization | Automation | BTI | Bitcell Design | Body Bias | CDL | DFT | DRC | Dual Port RAM | EM Reliability | Embedded memory | Embedded memory design | FastSPICE | FastScan | FinFET | GDSII | HCI | LEF | LVS | Leakage Optimization | Linux | Memory compiler | Memory design | Monte Carlo | Monte Carlo Analysis | PPA analysis | Parasitic Extraction | Performance optimization | Perl | Power Integrity | Python | ROM | Read Write Assist | Redhawk | Redundancy and Repair | Register File | Reliability analysis | SCAN | SPICE | SRAM | Self Timed Circuits | Sense Amplifier | Silicon validation | Statistical Analysis | Sub 7nm | TCL | Tessent | VLSI Design | Verilog | Vmin Optimization | Write Assist | Write Driver | Yield Optimization
Education
Roles
Design Lead | Embedded Memory Design Lead | Lead | Manager | Memory Design Lead | Senior Manager
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