Senior Quantum Design Verification Engineer
Tasks
- Align verification methodologies with cross functional teams
- Collaborate with Design for Test team
- Create testplans for digital and analog components
- Define verification plans for SoC and IP
- Drive continuous improvement of verification processes
- Drive milestone reviews and status reporting
- Manage bug tracking and issue resolution
- Own verification environments and tests
- Perform analog mixed signal simulation
- Setup verification databases and flows
- Validate designs in simulation pre and post layout
Perks/Benefits
- N/A
Skills/Tech-stack
Analog Mixed Signal modeling | Analog Mixed-Signal | Artificial Intelligence | Automation | C# | C++ | Chip Design | DFT | Data Analysis | Design for test | MATLAB | Mixed signal | Mixed-signal modeling | Netlists | Perl | Python | RTL | Register Transfer | Register Transfer Level | Ruby | Signal modeling | Simulation | SoC verification | Stimulus generation | Studio Code | TestBench | Visual Studio | Visual Studio Code
Education
Bachelor of Engineering | Bachelor of Science | Master of Science | PhD
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