Verification Engineer Intern
US Headquarters, United States
USD 88K-110K (estimate) Entry-level Full Time Internship
Tasks
- Collect simulation statistics
- Create tools scripts and utilities for simulation stimulus analysis
- Develop random test generators
- Develop test benches
- Implement coverage monitors checkers and assertions
- Measure simulation performance
- Write and debug tests and RTL logic
Perks/Benefits
- N/A
Skills/Tech-stack
Assembly | C# | C++ | Perl | Python | RTL | SystemVerilog | UVM | Verilog
Education
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