Staff Design Verification Engineer (AI/ML)
US, AZ, Chandler, East Elliot, United States
USD 127K-175K (estimate) Senior-level Full Time
Tasks
- Build SystemVerilog UVM testbenches
- Collaborate with design applications and test teams
- Conduct verification reviews and coverage analysis
- Develop verification strategies
- Drive coverage closure for tape out readiness
- Execute test planning through coverage closure
- Implement AI ML regression triage and anomaly detection
- Perform functional coverage analysis
- Support silicon correlation simulation to lab
Perks/Benefits
- N/A
Skills/Tech-stack
AI/ML | Back Annotation | Behavioral Abstraction | Cadence JasperGold | Cadence Xcelium | Clock Domain | Clock Domain Crossing | Domain crossing | Formal verification | Functional Coverage | Gate-level | Gate-level simulation | Layout Verification | Post-layout verification | Python | Real number modeling | SDF Back Annotation | SystemVerilog | SystemVerilog Assertions | UVM | Verilog-AMS
Education
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