Senior Design Verification Engineer, Multimedia/AI/ML, Silicon
Tasks
- Create constrained-random verification environments
- Debug verification failures
- Develop test plans
- Enhance UVM testbenches
- Identify verification scenarios
- Improve verification methodologies
- Make technical decisions
- Measure coverage metrics
- Plan multimedia block verification
- Represent DV status
Perks/Benefits
- N/A
Skills/Tech-stack
ACE | APB | ARM | AXI | Constrained random | Constrained random verification | Debugging | Formal verification | Interconnect protocols | Low power | Low power verification | Power Verification | Python | Random Verification | SoC verification | SystemVerilog | Test cases | UVM | Verification Test | Verification Test Cases | Verification testbench
Education
Regions
Countries
States
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