Director, Embedded Memory
USD 187K-292K (estimate) Executive-level Full Time
Tasks
- Allocate engineering effort and manage schedules
- Build competitive memory performance benchmarks
- Conduct root cause analysis and issue resolution
- Create customer technical collateral
- Define bitcell and peripheral architecture
- Drive presales customer technical engagements
- Drive what if and sensitivity analysis
- Establish design verification and signoff methodology
- Lead DFT scan and BIST repair
- Lead SPICE characterization and Monte Carlo analysis
- Lead circuit design and physical implementation
- Lead integration debug and silicon correlation
- Lead memory compiler architecture
- Lead mentor and grow memory design team
- Lead silicon validation and test chip development
- Optimize Vmin leakage performance area yield
- Own memory portfolio technical roadmap
- Perform PPA analysis and benchmarking
- Provide primary technical point of contact for customer integration
- Represent company at foundry partner meetings and conferences
- Set team technical goals and conduct reviews
- Translate SoC requirements into compiler specifications
Perks/Benefits
- N/A
Skills/Tech-stack
AI tools | Area Optimization | Automation | BTI | Bitcell Design | Body Bias | CDL | DFT | DRC | Decoder | Dual Port RAM | EM Reliability | Embedded memory | Embedded memory design | FastSPICE | FastScan | GDS | HCI | LEF | LVS | Leakage Optimization | Linux | Memory compiler | Memory design | Monte Carlo | Monte Carlo Analysis | PPA analysis | Parasitic Extraction | Performance optimization | Perl | Process variation | Process variation analysis | Python | ROM | Read Write Assist | Redhawk | Redundancy Repair | Register File | Reliability analysis | SCAN | SPICE | SRAM | Self Timed Circuits | Sense Amplifier | Silicon correlation | Statistical Analysis | TCL | Tessent | Testchip Definition | Variation analysis | Verilog | Vmin Optimization | Vmin Yield Modeling | Write Assist | Write Driver | Yield Optimization | Yield modeling
Education
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