Senior Manager, Embedded Memory
Montbonnot-Saint-Martin, Auvergne-Rhône-Alpes, France
EUR 55K-80K (estimate) Senior-level Full Time
Tasks
- Allocate engineering effort manage schedules dependencies and risk
- Conduct root cause analysis for customer reported issues
- Conduct technical reviews and set engineering goals
- Coordinate across design characterization CAD and product teams
- Define bitcell selection and peripheral architecture
- Develop customer ready PPA collateral
- Drive circuit design and physical implementation
- Drive presales customer engagements and technical workshops
- Establish design verification and signoff methodology
- Lead SPICE characterization and Monte Carlo analysis
- Lead integration debug and silicon correlation discussions
- Lead memory compiler architecture
- Lead mentor and grow memory design team
- Manage BIST repair DFT and physical verification
- Optimize Vmin leakage performance area yield
- Own silicon validation and test chip reporting
- Perform PPA analysis and competitive benchmarking
- Represent company in foundry partner meetings and industry conferences
- Run what if and sensitivity analysis for architecture trade offs
- Serve as primary technical point of contact for integration and validation
- Translate SoC requirements into compiler specifications
Perks/Benefits
- N/A
Skills/Tech-stack
Amplifier design | BIST | BTI | Bitcell Design | Body Bias | CDL | DFT | DRC | Dual Port RAM | EM | Embedded memory | FastSPICE | FastScan | FinFET | HCI | LVS | Leakage Optimization | Linux | Memory compiler | Memory compiler automation | Monte Carlo | PVT corners | Parasitic Extraction | Performance Area Yield Optimization | Perl | Physical Verification | Power Integrity | Power integrity signoff | Python | Python Scripting | ROM | RTL | Read Assist | Redhawk | Redundancy Repair | Register File | Reliability analysis | SDK automation | SPICE simulation | SRAM | Self Timing | Sense Amplifier | Sense-amplifier design | Silicon validation | Statistical Monte Carlo | Sub 7nm | TCL | Tessent | Test Chip | Verilog | Vmin Optimization | Write Assist | Write Driver | Yield Optimization
Education
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