RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead
Bangalore, Karnataka, India
INR 1500K-2500K (estimate) Senior-level Full Time
Tasks
- Collaborate with power and synthesis teams on timing power and datapath interactions
- Define block level design including interfaces clocking transaction flow and pipeline
- Develop RTL microarchitecture and coding strategies
- Develop assertions for white box testing coverage
- Drive lint CDC formal verification and UPF checks
- Lead RTL coding for subsystem and SoC integration
- Perform simulation debug for functionality and performance
- Work with stakeholders on design collateral quality and workarounds
Perks/Benefits
- N/A
Skills/Tech-stack
Assertions | CDC | DFT | Formal verification | Lint | Logic Design | Low power | Low power design | Microarchitecture | NOC design | Power analysis | Power design | RTL design | Simulation debugging | SoC integration | Synthesis | SystemVerilog | Timing Constraints | UPF | Verilog | Waveform debugging
Education
Bachelor of Engineering | Bachelor of Science | Master of Engineering | Master of Science | PhD
Roles
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