Validation/Verification (UVM, Coverage, Agentic), Staff Engineer
Tasks
- Benchmark AI verification solutions
- Collaborate with AI agents
- Define coverage strategies
- Drive verification closure
- Generate and debug tests
- Identify coverage gaps
- Own verification artifacts quality
- Provide feedback to AI tool teams
- Tag and contextualize verification data
- Validate AI-generated outputs
Perks/Benefits
- N/A
Skills/Tech-stack
AI Assisted Verification | Code Coverage | Coverage analysis | Debugging | Functional Coverage | Python | Scenario coverage | SystemVerilog | SystemVerilog Assertions | TCL | Testbench generation | UVM | Unix | VCS | VHDL | Verdi | Verilog
Education
Roles
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