Silicon Design Verification Engineer, Quantum AI
Mountain View, CA, USA; Goleta, CA, USA
USD 138K-198K Mid-level Full Time
Tasks
- Create and execute verification plans and test cases
- Debug verification failures
- Develop and maintain constrained-random verification environments
- Integrate verification IP from external vendors
- Plan verification for digital design blocks
- Track and close coverage metrics
Perks/Benefits
- N/A
Skills/Tech-stack
ARM | C-based testing | Chip verification | Constrained random | Constrained random verification | Ethernet | Formal verification | Mixed signal | Mixed-signal verification | NOC | PCIe | Perl | Python | RISC-V | Random Verification | Signal verification | System on Chip verification | System on chip | SystemVerilog | UVM | Verification coverage
Education
Bachelor of Engineering | Bachelor of Science | Master of Science | PhD
Regions
Countries
States
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