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Design Technology Co-Optimization Engineer

Sunnyvale, CA, USA

USD 138K-198K Mid-level Full Time

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Found 12h ago
Tasks
Perks/Benefits
Skills/Tech-stack

CMOS device physics | Datacenter IP blocks | Design Rule Manual | Design rule | Device physics | FinFET | Integrity analysis | Layout parasitics | Library Characterization | Metal Stack | Metal stack optimization | Nanosheet | PDK | Perl | Physical Design | Physical Verification | Place and route | Power Integrity | Power integrity analysis | Python | RTL Synthesis | Reliability analysis | Standard Cell Library | Standard Cell Library Characterization | Standard cell | Static Timing | Static Timing Analysis | TCL | Technology development | Timing Analysis

Education

Bachelor of Science | Master of Science | PhD

Roles

Design Technology Co-Optimization Engineer | Engineer | Optimization Engineer

Regions

North America

Countries

United States

States

California, US

Cities

Sunnyvale, California, US

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