Senior Member of Technical Staff, AI-optimized Memory SoC Microarchitect
Tasks
- Analyze IR drop budgets
- Analyze on die power delivery networks
- Analyze power grid topologies
- Define SoC floorplans
- Define SoC microarchitecture
- Define design for test architecture
- Define power delivery architectures
- Define scan chain topology
- Define signal interfaces
- Drive clocking architecture design
- Drive power sequencing design
- Estimate and optimize chip area
- Estimate and optimize chip energy
- Estimate and optimize chip performance
- Estimate and optimize chip power
- Estimate and optimize chip timing
- Identify power hotspots
- Maintain SoC microarchitecture documentation
- Mitigate thermal hotspots
- Set verification requirements
Perks/Benefits
- Dental insurance
- Income Protection for Illness or Injury
- Medical insurance
- Paid Holidays
- Paid family leave
- Paid time off
- Vision insurance
Skills/Tech-stack
Clocking | DFT | Delivery networks | Finite-state machines | Floorplanning | Grid Topology | ICC2 | IR-Drop | IR-drop analysis | Interconnects | Power Grid Topology | Power Hotspot Mitigation | Power delivery | Power delivery networks | Power grid | Power sequencing | Prime Power | Prime Shield | RTL | Redhawk | Scan chains | State machines | Static Timing | Static Timing Analysis | Synthesis | Thermal analysis | Timing Analysis
Education
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