Senior Engineer, Physical Design AI/ML
San Jose, California, United States
USD 138K-206K Senior-level Full Time
Tasks
- Assess and share findings with internal R and D teams
- Automate and accelerate clock tree synthesis
- Automate and accelerate design rule checks and layout versus schematic checks
- Automate and accelerate floor planning placement and routing
- Build and implement machine learning models to optimize chip layout for PPA efficiency
- Collaborate on exploratory PDK generation and automated QA systems
- Create internal benchmarking capability using modeling or learning
- Develop correlations across device and circuit data using machine learning
Perks/Benefits
- 401k
- Adoption support
- Charitable giving match
- Fertility care stipend
- Flexible work environment
- Holidays
- Medical travel support
- Medical/Dental/Vision
- On demand therapy sessions
- Onsite cafe
- Onsite gym
- Paid time off
- Sick leave
- Virtual fitness classes
- Virtual vet care
Skills/Tech-stack
Active Learning | Agentic AI | Bayesian optimization | C++ | Clock Tree | Clock Tree Synthesis | Deep learning | Design Kit | Design rule | Design rule checks | EDA Tools | Floor planning | Generative Models | Graph Neural Networks | Inverse design | Layout versus schematic | Library Characterization | Logic Cell Library Characterization | Machine Learning | Neural Networks | Place and route | Process Design | Process design kit | PyTorch | Python | RTL Synthesis | Regression | Surrogate modeling | TensorFlow | Timing Analysis
Education
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