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Validation/Verification (UVM, Coverage, Agentic), Staff Engineer

Hyderabad, India

INR 2000K-2372K (estimate) Senior-level Full Time

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Found 5h ago
Tasks
Perks/Benefits
Skills/Tech-stack

AI Assisted Verification | Code Coverage | Coverage analysis | Debugging | Functional Coverage | Python | Scenario coverage | SystemVerilog | SystemVerilog Assertions | TCL | Testbench generation | UVM | Unix | VCS | VHDL | Verdi | Verilog

Education

Bachelor of Science | Master of Science

Roles

Engineer | Staff Engineer | Verification Engineer

Regions

Asia/Pacific

Countries

India

States

Telangana, IN

Cities

Hyderābād, Telangana, IN

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