RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead
Bangalore, Karnataka, India
INR 1500K-2300K (estimate) Senior-level Full Time
Tasks
- Define block level design including interfaces and clocking
- Develop assertions for white box testing coverage
- Develop microarchitecture and coding strategies
- Generate design collaterals including timing constraints and UPF
- Implement RTL coding for subsystem and SoC integration
- Lead lint CDC FV UPF checks for design quality
- Perform function and performance simulation debug
Perks/Benefits
- N/A
Skills/Tech-stack
Assertion Language | CDC | Clocking | Computer system | Computer system architecture | Design for test | Formal verification | Lint | Logic Design | Low power | Low power design | Microarchitecture | NOC design | Pipeline | Power Intent Specification Language | Power design | Power intent | Register Transfer | Register Transfer Level | Simulation | Synthesis | System Architecture | SystemVerilog | Transaction flow | UPF | Verilog | Waveform debugging
Education
Bachelor of Engineering | Bachelor of Science | Master of Science | PhD
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