Senior Manager, Embedded Memory
Montbonnot-Saint-Martin, Auvergne-Rhône-Alpes, France
EUR 55K-72K (estimate) Senior-level Full Time
Tasks
- Conduct root cause analysis for customer issues
- Conduct what if and sensitivity analysis for architecture trade offs
- Coordinate with design characterization CAD and product teams
- Define bitcell and peripheral architecture
- Develop customer technical collateral datasheets and application notes
- Drive circuit design and physical implementation
- Establish design verification and signoff methodology
- Lead DFT BIST and repair implementation
- Lead SPICE and FastSPICE characterization
- Lead memory compiler architecture
- Lead presales customer engagements
- Lead silicon validation and test chip efforts
- Lead technical integration debug and silicon correlation
- Manage roadmap schedules dependencies and risks
- Mentor and grow memory design engineers
- Optimize Vmin leakage performance area yield
- Perform PPA analysis and competitive benchmarking
- Run Monte Carlo and statistical analysis
- Serve as primary technical contact for customers
- Set team goals and conduct technical reviews
- Translate SoC requirements into compiler specifications
Perks/Benefits
- N/A
Skills/Tech-stack
BTI | Bitcell Design | Body Bias | CDL | Circuit design | DFT | DFT Scan | DRC | Decoders | Dual Port RAM | EM | FastSPICE | FastScan | GDS | HCI | LEF | LVS | Linux | Memory compiler | Monte Carlo | Monte Carlo Analysis | Parasitic Extraction | Perl | Physical Implementation | Power Integrity | Power integrity signoff | Python | ROM | RTL Verilog | RTL modeling | Read Write Assist | Redhawk | Redundancy and Repair | Register File | Reliability analysis | SCAN | SPICE | SRAM | Self Timed Circuits | Sense Amplifier | Silicon correlation | Statistical Analysis | TCL | Tapeout | Tessent | Test Chip | Verilog | Vmin Yield Modeling | Write Assist | Write Driver | Yield modeling
Education
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