Technical Lead Manager, Machine Learning, Memory Subsystem Design
Tasks
- Collaborate with cross functional teams on development cycle
- Develop and validate DRAM subsystems including HBM
- Drive improvements to design methodologies processes and quality control
- Interface with DRAM manufacturers for design and validation
- Interface with third party IP providers for memory controllers and verification models
- Lead mentor and manage RTL design and DV engineers
Perks/Benefits
- N/A
Skills/Tech-stack
DRAM | DRAM controller | Design methodologies | Design verification | HBM | Memory subsystem | Memory subsystem design | Packaging | Physical Design | Physical layer | Power Integrity | Quality Control | RTL design | Signal Integrity | Silicon engineering | Silicon validation | Subsystem design | Verification models
Education
Regions
Countries
States
Cities
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